Welcome to /aig/ - Vaio edition
ITT we discuss non-x86 ISAs from the past (6502, 68000, Alpha, Itanium, PA-RISC, PowerPC, SuperH, VAX, Z80, PDP-11), the present (ARM, MIPS, POWER, SPARC) and the future (RISC-V, OpenPOWER).
You can also ask here for more information. Don't forget to check out the wiki, by the way!
>WIKI:
wiki.installgentoo.com
>Library:
mega.nz
>user's Strawpoll:
strawpoll.com
>OP pasta:
wiki.installgentoo.com
Previous Thread:
Other urls found in this thread:
electronicsweekly.com
embedded.com
linuxgizmos.com
powerpc-notebook.org
wiki.installgentoo.com
twitter.com
News:
>ARM
Record revenues at Arm - electronicsweekly.com
>RISC-V
MIPS pivots to RISC-V, targets high performance processing - embedded.com
Canaan RISC-V based development board targets AI applications - linuxgizmos.com
Also
>inb4 falseflag spammer faggot that claims everyone is OP because the thread is slow
Again, either contribute or GTFO and kill yourself you fucking nigger
dead general
PowerPC will be resurrected
powerpc-notebook.org
Purchased a SUN/ORACLE SPARC T3-1 and does anyone on earth know how to fucking control the fans on this thing. Yes it’s enterprise hardware but I’d expect there to be atleast some way
Welcome to the spam / bot post dead thread with no actual organic content
Well at least you had the decency to change your bot's message so that counts as organic content, you're a good boy :)
Just checked some manuals for it, there doesn't seem to be anything regarding controlling the fans
what is the most powerfull Alternative ISA laptop I can buy?
M1 Macs
god damnit
is ARM backdoored?
is that a joke?
non glownigger alternative ISA* then
So what is the benefit of an alternative ISA?
>Be MIPS I(tm)
>32 bit words
>j is a 32 bit instruction word with 6 bits for the opcode (0000 10) and 26 bits for the address to jump to, shifted two bits the left
>means you have limp dick, less than 2^32 PC addresses,
>you have to do mental gymnastics (bitshifting) if you want to calculate the instruction word by hand
>beq is a 32 bit instruction word with 6 bits for the opcode (0001 00) 5 bits for the source register (rs) and 5 bits for the target register (rt), which leaves us with 16 bits for the address
>but the 16 bits are not an address
>they are actually an offset
>they count how many instructions you have to jump ahead to reach your next instruction word
>if you want to calculate the instruction word by hand, you have to do mental gymnastics (count the instruction you have to skip)
Other than M1, probably a Chromebook
Checked and Cont.
>be MIPS I(tm)
>want to actually fill an entire register and not just the lower 16 bits
>you have to mental gymnastics to do that
>2 seperate instruction because limp dick (fixed instruction word size)
> ori $4, $4, 0xFFFF
>register 4 is now 0xFFFF0000
> addi $4, $4, 0xFFFF
>register 4 is now 0xFFFFFFFF
It never went away, it's just called Power now
And that is only if register 4 was actually 0x00000000, if not you have to
> xor $4, $4, $4
first and then continue. You could theoretically just do
> addi $4, $0, 0xFFFF
> ori $4, $4, 0xFFFF
and save one (in numbers: 1) instruction, but that would mean you're homosexual.
Thank you for reading my blog.
>wiki.installgentoo.com
Fix the wiki; it classifies PowerPC as CISC, but PPC is obviously RISC
Fix it yourself, it's a damned Wiki
I cant, I dont have internet
bros I bought 6 orange pi zeros for 15 bucks a pop. what do i do with them?
cluster
hotglue them